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1/14 june 1999 ? 1. introduction this application note shows an example of how to use st52x301 to communicate with an eeprom memory with an i 2 c bus protocol. in this example, an m24c04 eeprom (4k bit) is taken into account, but the following considerations can be applied to applications with any kind of m24cxx memory. two software routines are proposed, the byte write and the random read access, for st52x301 microcontroller configured in single master communication. 2. communicating protocol the m24cxx is an eeprom supporting the i2c protocol. the m24cxx can communicate with a microcontroller, the master, only by a serial data i/o line (sda) and a serial clock (scl). during each data transfer, the m24cxx samples the sda bus signal on the rising edge of the clock signal scl. the sda signal must be stable during the clock low to high transition and the data must change only when the scl line is low. changes in the data line while the clock is high are interpreted as a start and stop conditions. start is identified by a high to low transition of the sda line while the clock is stable in the high state. a start condition must precede any data transfer command. after the start, st52x301 sends onto the sda bus line 8 bits (msb first): the first 7 bits to select the device, the last (rw bit) to indicate if it is a read (rw high) or write (rw low) operation. after sending each 8 bits data stream, the master releases the sda bus; during the 9th clock pulse period the receiver pulls the sda bus low to acknowledge the receipt of the 8 bit data. a complete data transfer is always terminated by a stop, identified by a low to high transition of the sda line while the clock scl is stable in the high state. AN1146 application note i 2 c communication between st52x301 and eeprom authors: v. marino, c. vinci fig.1-i 2 c bus protocol
AN1146 - application note 2/14 3. hardware description the connection scheme between st52x301 and eeprom is shown in figure 2. pin p0 of st52x301 is used to transfer data to and from the memory (sda); pin p8 for data syncronization (scl). in this scheme m24c04 inputs e0, e1 and e2 are tied to vss (device select code is a0h), therefore, being e0 low, only 256 byte of memory, the low part, can be addressed. to address also the memory high part (address 1xxxxxxxx), e0 must be dynamically driven by using another i/o pin of st52x301. a maximum of four memories of the type m24c04 can be addressed by a microcontroller on the same two wire bus, setting e1 and e2 inputs (00, 01, 10, 11): each device is identified by its device select code and will only respond to the correct selection. pin wc, used to protect the contents of the memory from inadvertent erase/write operations, is unconnected, therefore with this scheme, write operations are always allowed. to allow enabling (wc\=v il ) and disabling (wc=v ih ) write operations, wc must be driven dynamically. fig. 2 - st52x301/eeprom i 2 c schematics 3.1 byte write mode in write mode, after the start condition, st52x301 sends a device select code with the rw} bit set to 0, as shown in figure 3. the memory acknowledges the reception and waits for an address byte from the master, to which it responds with an acknowledge. after the acknowledge, st52x301 sends the data byte to be written in the defined memory location. st52x301 terminates the transfer by generating a stop condition. start stop fig, 3 - byte write mode sequences with wc=0 (data write enabled)
i 2 c communication between st52x301 and eeprom 3/14 3.2 random address read mode in order to read a byte from an address of the memory, st52x301 performs a dummy write to load the address, as shown in figure 4. then, without sending a stop condition, st52x301 sends another start condition and resends the device select code, with the rw\ bit set to 1. after acknowledgment, the memory provides onto the bus the contents of the addressed byte. the master is not required to acknowledge the byte output and terminates the transfer with a stop condition. start start start stop fig. 4 - read mode sequence 4. software (i 2 c communication routines between st52x301 and m24c04 eeprom) the software project for st52x301 communicating with an eeprom m24c04 is described in the followings. two routines are developed with fuzzystudio tm 3.0 to show how to perform operations of write and read of a single byte at a specific address. to manage more bytes, a simple modification of this program must be done. fig. 5 - main window
AN1146 - application note 4/14 4.1 byte write software routine the main flow chart program of st52x301 wryte byte routine, as developed in fuzzystudio tm 3.0 environment, is shown in figure 5. after the block initialize , where the communication speed, the address and the value of the byte to write are set, the start condition is performed in the block start bit . then three bytes are serially sent onto sda bus, respectively the device select code, the address byte and the data byte to be written into the memory address location: after each byte is sent, st52x301 waits for m24c04 acknowledgement; at each ack receipt, the variable cont_ack , initially set to zero, is incremented of one unit. when cont_ack reaches 3, a stop condition is sent by st52x301 to the memory. if the signal ack is not returned from the memory, the program provides to restart the communication protocol. 4.1.1 initialize block this block allows to enable the timer interrupt, to set the timer counter and to initialize the variables (figure 6). the timer peripheral has been configured in order to have a timer cloc k t = 0.4ms by setting the prescaler value equal to 3 and the master clock frequency to 10mhz. the choice to load the counting from the the timer_count register, where the user can write values ranging from 10 to 255, allows to set the communication speed within the range [250khz ( fast mode ), 9.8khz ( standard mode )]. fig. 6 - peripheral initialization
i 2 c communication between st52x301 and eeprom 5/14 4.1.2 start_bit block this block performs the start condition: at first, the sda line is pulled in high state through sending of the number 1 into the parallel port (block data_high); then the scl line is pulled high by setting pin p8 high (block clk_high); finally sda is put low to complete the start bit communication, as required from the protocol (figure 2). time delays among transitions between each block in the start_bit routine are managed thanks to the timer peripheral. in fact each block is performed only after each timer count end: each wait block allows this synchronization waiting for the timer interrupt generated on the falling edge of the timer out signal. 4.1.3 send block to decide whether the device select code byte (160 in this case), or the address byte or the data byte must be sent (in the arithmetical block byte_to_send) the variable cont_ack is used (figure 7). to send each byte, bit by bit, a cycle scanned by a cont variable (incremented from 0 to 7) is performed. at each step of the cycle, one data bit is sent onto sda bus (in the sda block) and the scl line put low to high and again to low ( clock2 block), through port p8, to let the memory read the single bit data on the rising edge of scl clock signal pulse. the block bit_byte , written in assembler code for quick operations allows to send the single bit of the byte stream (see assembler code routine in appendix 1). fig. 7 - send block
AN1146 - application note 6/14 4.1.4 ack block after sending 8 bits data, st52x301 releases the sda bus, setting the pin p0 in input. reg_conf0 is used to set each pin of the parallel port in input or in output. during the 9-th clock pulse period, the eeprom pulls the sda bus low to acknowledge reception of the data byte: the byte read onto st52x301 parallel port is stored into an ack variable ( read_ack1 block). to understand if the lsb is 0 (on p0), therefore if the eeprom has correctly received the data, the 8 bit variable ack is masked. if p0 bit results to be 1, an error has occurred and the communication is restarted. fig. 8 - acknowledgement block
i 2 c communication between st52x301 and eeprom 7/14 4.1.4 stop_bit block a data transfer is always terminated by a stop condition, that is identified by a low to high transition of the sda line while the clock scl is stable in the high state. this condition is performed with the stop_bit block (figure 9). fig. 9 - stop block 4.2 read software routine the flow chart of the read memory routine, as developed with fuzzystudio tm 3.0 is shown in figure 10. after the block initialize , where the communication speed and the address of the byte to be read are set, the block start bit executes a start condition. three bytes are then sent serially onto sda bus. a cycle variable cont_ack is used to discriminate which byte is going to be sent: the device select code (160) if cont_ack is 0 the address byte if it is 1, the device select code again with the rw\ bit set to 1 (i.e. a byte corresponding to 161), after a new start condition, if cont_ack is 2. if cont_ack is 3, the data is read and the stop condition is executed. after each byte is sent, the microcontroller waits an acknowledgement from the memory: if the ack is not returned, the program provides to restart the communication protocol.
AN1146 - application note 8/14 4.2.1 read_data block to read the eigth bit data sent from the memory, st52x301 performs a cycle scanned by a variable cont : at each step cont is incremented from 0 to 7 and one bit of the data is received into pin p0 (block receive0) after the rising edge of the clock scl (pin p8 of st52x301). the block bit_data allows to build the data byte contained in the addressed location from each bit received from the memory (see appendix 2 for assembler code). fig. 10 - read_data block 4.2.2 send_ack block in accordance with the i 2 c communicating protocol, at the end of the data byte receipt, st52x301 puts the pin p0 high, before sending the stop condition. fig. 11 - send_ack block
i 2 c communication between st52x301 and eeprom 9/14 appendix 1 bit_byte assembler block this block is designated to write the data byte into the memory; the data is composed of eigth bits, then, in order to write it, a cycle of eight steps is realized (fig.7). at the first step the cycle counter cont is 0, then intruction send_byte_bit_7 is executed and the program jumps to label out ; at the second step, since cont is 1, the intruction send_byte_bit_6 is executed before jumping to label out , and so on. at this point, at label out , the variable mask contains one value among 128, 64, 32, 16, 8, 4, 2, 1. a logical and betwen the variables mask and send_byte will allow to determine i fa0ora1 data bit must be sent onto p0 by block sda (fig.7). the variable data contains the bit to be written. in this manner data is converted from parallel to serial format. //************************************************************************** ldrc temp 0 sub temp cont jpnz a0 //cont!=0 //******send_byte-bit7***** ldrc mask 128 //cont=0 jp out //************************ a0: ldrc temp 1 sub temp cont jpnz a1 //cont!=1 //******send_byte-bit6***** ldrc mask 64 //cont=1 jp out //************************ a1: ldrc temp 2 sub temp cont jpnz a2 //cont!=2 //******send_byte-bit5***** ldrc mask 32 //cont=2 jp out //************************
AN1146 - application note 10/16 a2: ldrc temp 3 sub temp cont jpnz a3 //cont!=3 //******send_byte-bit4***** ldrc mask 16 //cont=3 jp out //************************ a3: ldrc temp 4 sub temp cont jpnz a4 //cont!=4 //******send_byte-bit3***** ldrc mask 8 //cont=4 jp out //************************ a4: ldrc temp 5 sub temp cont jpnz a5 //cont!=5 //******send_byte-bit2***** ldrc mask 4 //cont=5 jp out //************************ a5: ldrc temp 6 sub temp cont jpnz a6 //cont!=6 //******send_byte-bit1***** ldrc mask 2 //cont=6 jp out //************************
i 2 c communication between st52x301 and eeprom 11/14 a6: ldrc temp 7 sub temp cont jpnz out //cont!=7 //******send_byte-bit0***** ldrc mask 1 //cont=7 //************************ out: ldrc data 0 and mask send_byte jpz b0 ldrc data 1 b0: //**************************************************************************
AN1146 - application note 12/14 appendix 2 bit_data assembler block this block is designated to read the data from the memory; the data is composed of eigth bits, then, in order to read it, a cycle of eigth step is realized(fig.11). at the first step the cycle counter cont is zero, then the intruction data-bit7 is executed and the program jumps to label out ; at the second step, the intruction data-bit6 is executed before jumping to label out, and so on. at this point, at label out , the variable mask contains one value among 128, 64, 32, 16, 8, 4, 2, 1; if at step n of the eight bit cycle, the variable read_bit is 1, the variable data is increased adding the variable mask contents. in this manner data is converted from serial to parallel format. //************************************************************************** ldrc temp 1 and read_bit temp //read_bit will contain ?0? or ?1? ldrc temp 0 sub temp cont jpnz c0 //cont!=0 //******data-bit7***** ldrc mask 128 //cont=0 jp out //************************ c0: ldrc temp 1 sub temp cont jpnz c1 //cont!=1 //******data-bit6***** ldrc mask 64 //cont=1 jp out //************************ c1: ldrc temp 2 sub temp cont jpnz c2 //cont!=2
i 2 c communication between st52x301 and eeprom 13/14 //******data-bit5***** ldrc mask 32 //cont=2 jp out //************************ c2: ldrc temp 3 sub temp cont jpnz c3 //cont!=3 //******data-bit4***** ldrc mask 16 //cont=3 jp out //************************ c3: ldrc temp 4 sub temp cont jpnz c4 //cont!=4 //******data-bit3***** ldrc mask 8 //cont=4 jp out //************************ c4: ldrc temp 5 sub temp cont jpnz c5 //cont!=5 //******data-bit2***** ldrc mask 4 //cont=5 jp out //************************ c5: ldrc temp 6 sub temp cont jpnz c6 //cont!=6 //******data-bit1***** ldrc mask 2 //cont=6 jp out //************************
AN1146 - application note 14/14 c6: ldrc temp 7 sub temp cont jpnz out //cont!=7 //******data-bit0***** ldrc mask 1 //cont=7 //************************ out: and read_bit read_bit jpz d0 add data mask d0: //************************************************************************* information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved fuzzystudio tm is a registered trademark of stmicroelectronics stmicroelectronics group of companies http://www.st.com australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco -the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a.

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